Doctoral Thesis Oral Defense - Kaiyang Zhao

July 13, 2026  10:00AM—12:00PM

Location:
4405 & Zoom - Gates and Hillman Centers

Speaker:
KAIYANG ZHAO, Ph.D. Candidate, Computer Science Department, Carnegie Mellon University
https://www.cs.cmu.edu/~kaiyang2/

Architecting Memory Efficiency in Modern Data Centers

Modern datacenter computing faces a critical memory bottleneck driven by memory-intensive applications, terabyte-scale memory capacities, and slowing DRAM technology improvements. The memory bottleneck manifests in multiple dimensions including access performance, hardware costs, and power consumption.

First, the virtual memory abstraction is under increasing strain, where stagnant Translation Lookaside Buffer sizes relative to growing memory capacity cause severe and escalating virtual address translation overheads. Second, the hardware costs and power consumption of memory hardware have skyrocketed as DRAM now accounts for nearly 25% of rack power consumption and 50% of a server’s Total Cost of Ownership. This thesis addresses these challenges through the co-design of OS and architectures.

To reduce the overhead of virtual memory, my research targets the virtual address translation overhead with two works. Contiguitas groups unmovable allocations in the OS and introduces hardware extensions to migrate device I/O pages. By creating abundant physical memory contiguity, it allocates more huge pages, yielding up to an 18% performance improvement for Meta’s production workloads. Learned Virtual Memory replaces rigid radix page tables with learned page tables tailored to application virtual address spaces. LVM balances the size, depth, and accuracy of learned index, reducing page walk overheads by an average of 44% and achieving a 2-27% execution speedup. To reduce memory cost and power, my research enables the practical deployment of tiered CXL memory in datacenters with two works. Pensieve is a three-tier memory system (DRAM, CXL, and SSD) that transparently manages data placement via a single-input single-output control loop. It leverages CXL memory as an intermediate tier to safely offload 33% of memory while keeping performance degradation under 5%. Equilibria addresses multi-tenant challenges by ensuring fair sharing of tiered memory and mitigating noisy-neighbor effects. It provides automatic fair-share determination and thrashing mitigation, boosting performance over the state-of-the-art Linux solution by up to 52% for Meta’s workloads and 1.7x for DCPerf, a representative benchmark for datacenter workloads.

Together, these works significantly optimize datacenter memory efficiency through a comprehensive set of architectural and operating system techniques and lay the foundation for sustainable memory scaling for years to come.

Thesis Committee: 
Dimitrios Skarlatos (Chair)
Phillip Gibbons
Todd Mowry
Kim Keeton (Google)

In-person and Zoom

Contact
Matt Stewart


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