Michael K. Papamichael

Pandora: Facilitating IP Development for Hardware Specialization Degree Type: Ph.D. in Computer Science
Advisor(s): James Hoe
Graduated: August 2015

Abstract:

In an effort to continue increasing performance in the power-constrained setting of the post-Dennard era, there is growing interest in hardware specialization. However, a major obstacle to the more widespread use of hardware acceleration is the level of difficulty in hardware design today. Despite the increased availability of rich IP libraries and even IP generators that span a wide range of application domains, developing hardware today is limited to experts, takes more time and is more expensive than ever.

This thesis presents the Pandora IP development paradigm that facilitates hardware development and specialization by extending the concept of generator-based IPs. Pandora encapsulates the IP author's expertise and domain knowledge to offer supporting infrastructure and assist the users' interactions with the IP. In contrast to existing IPs and IP generators that only capture the structural and microarchitectural view of a design, Pandora argues for augmenting IPs with: (1) detailed IP design space characterization to help the user understand the effects of parameter choices with respect to hardware implementation and IP-specific metrics, (2) application-level goal-oriented parameterization that is meaningful to the IP user and automatically sets low-level structural parameters to achieve the desired design optimizations, and (3) purpose-built domain-aware simulation-time and run-time monitoring mechanisms to assist functional and performance debugging.

To highlight the benefits of hardware specialization and demonstrate the key principles of the Pandora IP development paradigm, this thesis presents our research efforts on: (1) CONNECT, a flexible Network-on-Chip (NoC) IP generator that embodies the Pandora principles and is actively used by hundreds of researchers around the world, (2) DELPHI, a framework for fast easy IP characterization that facilitates mapping the design space of arbitrary RTL-based IPs, (3) Nautilus, an IP optimization engine that demonstrates how incorporating IP author knowledge in genetic algorithms can enable very fast-orders of magnitude faster than conventional methods-highlevel goal-oriented IP optimization, and (4) IRIS, an instrumentation and introspection framework that combines hardware monitors with software-based post-processing and visualization engines to accelerate debugging of complex IPs and enable higher system-level visibility.

Thesis Committee:
James C. Hoe (Chair)
Ken Mai
Todd Mowry
Onur Mutlu
Mark Horowitz (Stanford University)

Frank Pfenning, Head, Computer Science Department
Andrew W. Moore, Dean, School of Computer Science

Keywords:
Computer Architecture, Network-on-Chip, NoC, FPGA, ASIC, Reconfigurable Hardware, Hardware Specialization, Hardware Acceleration, IP Block, IP Development, IP Optimization, Design Space Exploration, Hardware Instrumentation, Runtime Monitoring