SCS Distinguished Industry Lecture

— 1:00pm

In Person - Newell-Simon 4305

DEBENDRA DAS SHARMA , Intel Senior Fellow, Chief Architect, I/O Technology and Standards
Director, PCI-SIG Board
Co-chair CXL Board Technical Task Force, CXL Consortium;
Chair of the Universal Chiplet Interconnect Express (UCIe) Consortium

Compute Express Link (CXL*): Changing the compute landscape

High-performance workloads demand heterogeneous processing, tiered memory architecture, infrastructure accelerators such as SmartNICs, and infrastructure processing units to meet the demands of the emerging compute landscape. Applications such as artificial intelligence, machine learning, data analytics, 5G, automotive, and high-performance computing are driving significant changes within cloud computing, intelligent edge and client computing infrastructure. Interconnect is a key pillar in this evolving computational landscape. The recent advent of Compute Express Link (CXL), a new open standard for cache-coherent interconnect, with its memory and coherency semantics has made it possible to pool computational and memory resources at the rack level using low-latency, higher-throughput, and memory-coherent access mechanisms. CXL is adopting networking features such as multi-host connectivity, pooled memory, persistence flows, and fabric managers while keeping its low-latency load-store semantics intact. The load-store I/O interconnects such as PCI Express (PCIe) and CXL are evolving to provide efficient access mechanisms across multiple nodes with advanced atomics, acceleration, SmartNICs, persistent memory support, etc. In this talk we will explore how synergistic evolution across load-store interconnects and fabrics can benefit the compute infrastructure of the future. — Dr. Debendra Das Sharma is an Intel Senior Fellow in the Data Platforms and Artificial Intelligence Group and Chief Architect of the I/O Technology and Standards at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. Das Sharma’s team delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect. He is a key driver of external standards for PCIe, CXL, and UCIe, and internal proprietary interfaces, as well as implementation. Das Sharma joined Intel in 2001 as a technical lead in the Advanced Components Division, designing server chipsets. He previously worked with Hewlett-Packard, where he led development of their server chipsets. He holds 148 US patents. He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the Hot Interconnects, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Intel Developer Forum. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019. He has also been awarded the 2021 IEEE Region 6 Outstanding Engineer Award.

Event Website:

For More Information:

Add event to Google
Add event to iCal