Monday, December 6, 2021 - 1:00pm
Location:In Person and Virtual ET Gates Hillman 8102 and Zoom
Speaker:GRAHAM GOBIESKI, Ph.D. Student https://g-ram.github.io/
Ultra-low-power, Energy-minimal Computer Architectures
Ultra-low-power (ULP) sensor devices are increasingly being deployed for a variety of use-cases in many different environments. The applications are wide-ranging and growing in complexity, relying on sophisticated techniques like on-device machine inference and advanced digital signal processing. However, existing systems suffer fundamental inefficiencies in supplying instructions and data that demand solutions across the compute stack: from software that enables sophisticated workloads on ULP devices to new, energy-minimal computer architectures.
The objective of this work is to design a complete system stack that leverages new execution models to maximize energy-efficiency without sacrificing programmability. Specifically this thesis contributes 1) SONIC, a software-runtime system that enables DNN inference on intermittent, embedded devices, 2) MANIC, an ultra-low-power vector-dataflow co-processor, 3) SNAFU, a energy-minimal CGRA generation framework and architecture, and 4) MANIC silicon, a silicon prototype of the MANIC co-processor. Taken together these systems form the foundation of a new stack with state-of-the-art energy efficiency, making sophisticated workloads practical, and support for programmability, allowing for iteration, development of new algorithms, and quick deployment.
Finally, to round out the new system stack, this work will discuss the ongoing characterization of the MANIC silicon prototype and the development of a new dataflow compiler to target SNAFU-like CGRAs.
Nathan Beckmann (Co-Chair)
Brandon Lucia (Co-Chair)
Tony Nowatzki (University of California, Los Angeles)
In Person and Zoom Participation. See announcement.